AHA4701

Features and deliverables for the AHA4701 Low Density Parity Check Code (LDPC) core include:

Features

• Maximum date rate is 30 Mbits/sec for 3/4 code rate in Altera Stratix 30 FPGA
• Block sizes up to 30 Kbits
• Input quantization up to 6 bits
• Programmable up to 256 iterations per block
• Compact, area efficient, low power
• Supports "code-change-on-the-fly" allowing adaptation to changing channel conditions
• Exact code rate matching is possible
• Field re-programmability that supports multiple code rates and block sizes
• Fully synchronous design style
• Configurable design allows trade-offs between error rate performance and data rate
• Internal buffering allows flexible data interface

Deliverables

• Altera Stratix 30 SOF/POF files or Altera Stratix netlist
• Test bench and a complete functional verification suite
• Complete documentation

Low Density Parity Check Codes

Presentations

• Low Density Parity Check Products Overview

• Comtech AHA Announces 30 Mbps Low Density Parity Check Code (LDPC) Encoder/Decoder Core
• Comtech EF Data Chooses Comtech AHA Low Density Parity Check Code (LDPC) Technology for CDM-600 Satellite Modems

• AHA4701 Brief - 30 Mbits/sec LDPC Encoder/Decoder Core

• AHA4701 Specification - 30 Mbits/sec LDPC Encoder/Decoder Core

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